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MITSUBISHI
M56694FP/GP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
DESCRIPTION
The M56694 is a semiconductor integrated circuit that has a builtin, 32-bit shift register and a latch of CMOS structure with serial input and serial/parallel output, and a 32-bit totem-pole-type parallel output driver of high pressure proof DMOS structure.
PIN CONFIGURATION (TOP VIEW)
33 HVO12
32 HVO13
31 HVO14
30 HVO15
29 HVO16
28 HVO17
27 HVO18
26 HVO19
25 HVO20
24 HVO21 26 HVO21
Employed are Bi-CMOS and high pressure proof DMOS processing technology.
HVO11 HVO10 HVO 9 HVO 8 HVO 7 HVO 6 HVO 5 HVO 4 HVO 3 HVO 2 HVO 1
34 35 36 37 38 39 40 41 42 43 44
23 HVO22 22 HVO23 21 HVO24 20 HVO25 19 HVO26 18 HVO27 17 HVO28 16 HVO29 15 HVO30 14 HVO31 13 HVO32 12 PGND 25 HVO22 24 N.C 23 N.C 22 HVO23 21 HVO24 20 HVO25 19 HVO26 18 HVO27 17 HVO28 16 HVO29 15 HVO30 14 HVO31 13 HVO32
FEATURES
q Serial input-serial/parallel output q Cascade connections possible through serial output q Latch circuit included for each stage q Driver section supply voltage: VH=120V q Operating temperature: -20 - 75C
M56694FP
APPLICATION
Vacuum Fluorescent Display ANODE DRIVER
PGND VH SIN BLK LAT
FUNCTION
The M56694 comprises a 32-bit D type flip-flop with 32 latches connected to its output. In accordance with truth table 1, inputting data to SIN and clock pulse to CLK allows SIN signal to be put into the internal shift register when the clock changes from "H" to "L", and simultaneously shift register data to be shifted sequentially. Serial output SOUT is used by connecting to the next stage
Outline 44P6N-A (FP)
35 HVO12
34 HVO13
33 HVO14
32 HVO15
31 HVO16
30 HVO17
29 HVO18
28 HVO19
in the series. In accordance with truth table 2, parallel output allows the latch to pass data through if LAT input is turned to "H", and data to be retained if LAT input is turned to "L". Driver output HVOn allows data from the latch to be output if BLK input is turned to "L", and "L" to be output if BLK input is turned to "H", irrespective of data from the latch.
N.C HVO11 HVO10 HVO 9 HVO 8 HVO 7 N.C HVO 6 HVO 5 HVO 4 HVO 3 HVO 2
37 38 39 40 41 42 43 44 45 46 47 48
36 N.C
M56694 SIN when more than one M56694 is used to expand bits
M56694GP
10
27 HVO20
11
Outline 48P6D-A (GP)
N.C: no connection
PGND 12
1
2
3
4
5
6
7
8
HVO 1 PGND
VH SIN BLK LAT CLK LGND VDD SOUT VH
9
VDD 9 SOUT 10 VH 11
1
2
3
4
5
6
7
CLK LGND N.C
8
MITSUBISHI
M56694FP/GP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
BLOCK DIAGRAM (Note : Pin No. in paretheses are of M56694GP)
HVO 1
(1)
Output protect circuit
HVO 2
(48) 43
HVO 3
(47) 42
HVO30
15 (15)
HVO31
14 (14)
HVO32
13 (13) 2 11
44
VH
(3)(11)
VDD
(9)
9
1
PGND
12 (2)(12)
BLK
(5)
4
Q LD LAT
(6) 5
Q LD
Q LD
Q LD
Q LD
Q LD
7
LGND
(8)
SIN
(4)
3
DQ T
DQ T
DQ T
DQ T
DQ T
DQ T
10 SOUT (10) 8
CLK
(7)
6
N.C
(23)(24)(36) (37)(43)
TRUTH TABLE Truth table 1. Shift register section
CLK H or L Shift register operation DATA is shifted. No changes.
Truth table 2. Latch and driver sections
Dn X H L X LAT X H H L BLK H L L L HVOn Output all "L" H L Latch's data output. Dn=nth bit DFF retention data HVOn=nth bit driver output L="L" level H="H" level X="L" level or "H" level
MITSUBISHI
M56694FP/GP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
PIN FUNCTION DESCRIPTION
Pin name VDD LGND VH PGND CLK SIN SOUT LAT BLK HVO1 - 32 Function Logic stage supply voltage Logic stage ground Output stage supply voltage Output stage ground Clock input for the internal shift resister. The data enter the internal shift resisters and the data in the shift registers will be shifted in order by High to Low change of the clock. Serial data input Serial data output Latch input. When the LATCH is set to "H", the data in the shift resister will enter the each latch circuit. When the LATCH input is set to "L", the data will be held. Enable input for output control. When the BLK input is set to "L", data in the latch circuit will appear at outputs. When the BLK input is set to "H", all outputs will be set to "L". Output driver (push-pull)
ABSOLUTE MAXIMUM RATINGS (Ta=25C, unless otherwise noted)
Symbol VDD VH VI VO VHVO Pd Tstg Parameter Logic stage supply voltage Output stage supply voltage Logic inputs voltage Logic outputs voltage Output voltage Power dissipation range Storage temperature range Conditions Ratings -0.3 - 7 -0.3 - 120 -0.3 - VDD+0.3 -0.3 - VDD+0.3 -0.3 - VH 940 -55 - 150 Unit V V V V V mW C
Data output High supply voltage output pin Ta 25C
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VH Topr Parameter Supply voltage Supply voltage Operating temperature Conditions Ratings 4.5 - 5.5 10 - 110 -20 - 75 Unit V V C
ELECTRICAL CHARACTERISTICS (VDD=5V, VH=110V and Ta=25C, unless otherwise noted)
Symbol IDD IH IIH IIL VHVOH VHVOL VOH VOL IHVOH IHVOL VTH VTL Parameter Supply current 1 Supply current 2 "H" input current "L" input current Driver output voltage Logic output voltage "H" output current "L" output current Output protect operating voltage Test conditions No load Output all "L", no load Output all "H", no load Input pin VIH=5V SIN, LAT, CLK VIL = 0V BLK IHVOH = -0.5mA IHVOL = 0.5mA IOH = -0.1mA IOL = +0.1mA High supply voltage output pin High supply voltage output pin Min. Limits Typ. 1 0 2 0 0 100 4.5 -20 106 0.7 4.95 0.04 -1 1 3.4 3.1 Max. 2 50 4 2 -2 -100 2 0.4 -3 3 Unit mA A mA A A A V V mA mA V V
MITSUBISHI
M56694FP/GP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
SWITCHING CHARACTERISTICS (VDD=5V, VH=110V and Ta=25C, unless otherwise noted)
Symbol fCLK t PLH(SO) t PHL(SO) t PLH(OUT) t PHL(OUT) t rout t fout Parameter Clock frequency Logic output propagation time Driver output propagation time Driver output rise and fall time Test conditions Duty = 45 - 55% CL = 15pF 120 100 1 0.16 1.3 0.35 Min. Limits Typ. Max. 8 300 300 2 1 2.5 2 Unit MHz ns ns s s s s
RO = 220K CO = 50pF
TEST CIRCUIT
input VDD VH (1) Pulse generator characteristics tr20ns tf20ns (2) Capacitance CL includes connection floating capacitance and probe input capacitance. : RO=220K : CO=50pF
SOUT PG DUT CL HVOn 50
CO
RO
TIMING WAVEFORM
1/fmax CLK
50% 50% 50%
SIN
50%
50%
tsu tfso SOUT
90% 50% 10% 10%
th trso
90% 50%
tPHL(SO) tPLH(SO)
50%
BLK
50%
trOUT HVOn
10% 90% 50% 90% 50%
tfOUT
10%
tPLH(OUT)
tPHL(OUT)
MITSUBISHI
M56694FP/GP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
TYPICAL CHARACTERISTICS
Thermal derating
1.0 0.94 "H" output current IOH(mA) Power dissipation Pd(W) 10
Driver output VON-IOH
Ta=+75C
8
Ta=+25C Ta=-20C
6
0.5
4
2
0
0 0 25 50 75 100 0 2 4 6 8 10 Temperature Ta(C) "H" output voltage VON(V)
Duty cycle vs Permissible output current
10 9 1 - 13 14 10 9
Duty cycle vs Permissible output current
1-8 9
Output current IOH(mA)
8 7 6 5 4 3 2 1 0 0 20 40 60 80 100
Output current IOH(mA)
16
8 7 6 5 4 3 2 1 0 0 20 40 60 80 100 24 32 16
24 32
Duty cycle (%) Note * Ta=25C * Repeated frequency >100Hz * Figure in the circle represents the number of concurrently operating output circuits. * Current value denotes a numerical value per circuit.
Duty cycle (%) Note * Ta=75C * Repeated frequency >100Hz * Figure in the circle represents the number of concurrently operating output circuits. * Current value denotes a numerical value per circuit.
Note 1. VDD=5V and VH=110V, unless otherwise noted 2. Thermal derating characteristics represent those of an individual IC unit. 3. Allowable duty cycle output current characteristics represent that when a standard substrate is mounted. (Standard substrate: 70x70x1.6mm glass epoxy)

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